Wichtige Informationen
Intel is evolving its EMIB and Foveros packaging technologies to scale high-end CPU and GPU designs. By integrating these methods, Intel aims to build complex system-in-packages (SiPs) that scale both horizontally and vertically, moving beyond traditional silicon interposers to support massive AI and data center workloads.
EMIB technology is advancing through finer interconnect pitches and the introduction of EMIB-T, which incorporates through-silicon vias for improved power delivery. Intel expects EMIB-T to reach high-volume production in 2027. Future iterations may utilize glass-core substrates to enhance stability for packages reaching 12 times the size of a reticle.
The Foveros family now includes 2.5D and 3D integration options. Foveros Direct 3D, featured in the Xeon 6 'Clearwater Forest' processor, utilizes copper-to-copper hybrid bonding to achieve sub-10 µm pitches. This method eliminates solder bumps, improving thermal dissipation and signal density compared to conventional microbump-based stacking.
Intel's EMIB 3.5D architecture combines these technologies, linking vertically stacked modules laterally via EMIB bridges. While this approach enables massive heterogeneous integration, Intel opted against using EMIB 3.5D for its upcoming 'Diamond Rapids' Xeon processor, favoring UCIe-S for lateral connections instead.
